Field of the Invention
The present invention relates to a power control technique in an array-type processing device which includes a plurality of processing elements and can execute a plurality of different processes.
Description of the Related Art
Along with element miniaturization due to the advance of semiconductor manufacturing technologies, a scale of an LSI (Large-Scale Integrated circuit) is further increased, and the number of transistors to be mounted is exponentially increased. Then, an LSI which can cope with multiple applications by a single chip is demanded. High performance, low power consumption, and function change flexibility are especially required for an LSI so as to cope with a variety of products.
In recent years, in order to meet requirements such as high performance, low power consumption, and function change flexibility, an array-type processing device as a dynamically reconfigurable processor has received a lot of attention. The array-type processing device is mainly configured by processing elements (to be referred to as PEs hereinafter) such as a CPU, DSP, and ALU, and a router required to control inter-PE connections. Setting data called configuration information is set in the PEs and router to change the processing contents of the PEs and connections of the router. That is, by dynamically changing the configuration information according to the data processing contents, the array-type processing device can flexibly cope with function changes, and high performance can be easily attained by increasing the number of PEs.
However, by increasing the number of PEs mounted on the array-type processing device, processing performance can be improved, but power consumption is unwantedly increased at the same time. Hence, a technique for allocating a domain where ON/OFF of a power supply can be switched (power shut off domain) in the array-type processing device, and reducing power consumption by shutting off the power supply to that domain is known. Also, Japanese Patent Laid-Open No. 2010-244238 (parent literature 1) discloses a technique for suspending/resuming an operation of a processing device array. More specifically, patent literature 1 discloses a technique which uses a buffer circuit which temporarily stores externally supplied data when an operation of a reconfigurable processing device array is suspended, and supplies the stored data to the reconfigurable processing device array when the operation is resumed.
However, when the power shut off domain is allocated in the array-type processing device, if power supply to a configuration information transfer bus as a transfer path of configuration information is shut off, the configuration information cannot be written. For this reason, upon rewriting the configuration information, power supply to the configuration information transfer bus is required, and power supply has to be made even to domains which do not include any PEs associated with processes to be executed. The technique described in patent literature 1 above merely suspends/resumes the operation of the processing device array, and cannot solve this problem. Furthermore, a time period required to rewrite configuration information is prolonged as the number of PEs is increased. When the configuration information is switched frequently, a time period of a performance drop caused by a long rewrite time period of the configuration information after the power supply is resumed is not negligible.